Augmented Sidewall Topology Simulation of Semiconductor Die
Rennier Rodriguez *
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.
Frederick Ray Gomez
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.
Edwin Graycochea Jr.
New Product Development and Introduction, STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.
*Author to whom correspondence should be addressed.
Abstract
The paper presents a modified design for wafer level semiconductor devices, using a CAD (computer-aided design) tool for visualization. The discussion provides a specialized manufacturing flow for the augmented die design through advanced wafer fabrication method and wafer cutting technique. Ultimately, the new package design would result for better visual inspection and interface anchoring between the device and the external board.
Keywords: Redistribution layer, sidewall design, silicon die, wafer level