Journal of Engineering Research and Reports

Aims: To review how hardware–software co-design can make tiny machine learning (TinyML) on microcontrollers not only efficient but also reliable and secure, to classify existing approaches by design objective and stack layer, and to propose an integrated framework and research agenda for dependable on-device intelligence.

Study Design: Narrative (non-systematic) review.

Methodology: Peer-reviewed journal articles and conference papers, supplemented by a small number of influential preprints, technical reports, standards and one book, were identified from IEEE Xplore, the ACM Digital Library, ScienceDirect, SpringerLink, arXiv and Google Scholar. Studies were included if they addressed machine learning on microcontrollers or reported a reliability or security technique or finding that transfers directly to such devices. The 61 sources retained, published between 1999 and 2026, were classified by design objective (efficiency, reliability, security), layer of the hardware–software stack, platform and type of evidence, and synthesised narratively.

Results: Co-design of network architectures, quantisation, kernels, memory scheduling and hardware has made image-, audio- and sensor-based inference feasible within kilobytes of memory and milliwatts of power. However, reliability and security are usually treated as separate afterthoughts. Fault-injection studies show that the impact of soft errors depends strongly on data representation, bit position and layer, and that low-cost measures such as activation range restriction and selective hardening can mitigate many silent data corruptions. However, most of this evidence comes from software fault injection, often on platforms other than microcontrollers. Security studies demonstrate that physical access enables electromagnetic side-channel recovery of model architectures, instruction-skip and bit-flip attacks that alter predictions, and model extraction through query interfaces. Recent laser fault-injection studies on Arm Cortex-M devices have demonstrated practical bit-flip attacks and the extraction of model parameters from flash memory, although under laboratory conditions. Hardware isolation, secure boot, authenticated updates, masking and control-flow protection are available but rarely evaluated together with accuracy, latency and energy.

Conclusion: Dependable TinyML requires reliability and security to be treated as first-class design objectives alongside accuracy and efficiency throughout the design, verification, deployment and operation lifecycle. Standardised fault and threat models, benchmarks that report robustness and security costs, and multi-objective co-design tools are the main priorities for future research. Because the evidence is heterogeneous and the review is narrative, these conclusions are indicative and should be confirmed by experimental validation of the proposed framework.