Lead Scratch Resolution through Wirebonding Process Optimization on QFN Packages

Main Article Content

Jonathan Pulido
Frederick Ray Gomez
Edwin Graycochea Jr.


With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents an improvement done in quad-flat no-leads (QFN) leadframe package to resolve the quantity of unit rejection due to leads scratch underneath the leadframe. Moreover, the reject manifestation was captured after wirebonding process. Parameter optimization particularly for the second bond with the combination of bond force and bond scrubbing parameters was done to totally eliminate this type of issue after wirebonding process. With the wirebonding process optimization and improvement done, a reduction of 95 percent of leads scratch occurrence was achieved.

QFN, leadframe, wirebonding, bond force, bond scrubbing.

Article Details

How to Cite
Pulido, J., Gomez, F. R., & Jr., E. G. (2020). Lead Scratch Resolution through Wirebonding Process Optimization on QFN Packages. Journal of Engineering Research and Reports, 15(1), 29-33. https://doi.org/10.9734/jerr/2020/v15i117136
Original Research Article


Geng H. Semiconductor manufacturing handbook. 2nd ed. McGraw-Hill Education, USA; 2017.

Doering R, Nishi Y. Handbook of semiconductor manufacturing technology. 2nd ed. CRC Press, USA; 2007.

Harper C. Electronic packaging and interconnection handbook. 4th ed. McGraw-Hill Education, USA; 2004.

Tan CE, Liong JY, Dimatira J, Tan J, Kok LW. Challenges of ultimate ultra-fine pitch process with gold wire & copper wire in QFN packages. 36th International Electronics Manufacturing Technology Conference. Malaysia. 2014;1-5.

Saha S. Emerging business trends in the semiconductor industry. Proceedings of PICMET '13: Technology Management in the IT-Driven Services (PICMET). USA. 2013;2744-2748.

Sumagpang Jr. A, Rada A. A systematic approach in optimizing critical processes of high density and high complexity new scalable device in MAT29 risk production using state-of-the-art platforms. Presented at the 22nd ASEMEP Technical Symposium, Philippines; 2012.

Lay Yeap L. Meeting the assembly challenges in new semiconductor packaging trend. 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium (IEMT). Malaysia. 2010;1-5.

Lall P, Deshpande S, Nguyen L. Reliability of copper, gold, silver, and pcc wirebonds subjected to harsh environment. IEEE 68th Electronic Components and Technology Conference (ECTC). USA. 2018;724-734.

Sumagpang Jr. A, Graycochea Jr. E, Gomez FR. Package design improvement for wire shorting resolution. Journal of Engineering Research and Reports. 2020;11(2):41-44.

Pulido J, Gomez FR, Graycochea Jr. E. Wirebond process improvement with enhanced stand-off bias wire clamp and top plate. Journal of Engineering Research and Reports. 2020;9(3):1-4.

Moreno A, Graycochea Jr. E, Gomez FR. Specialized wire bond process configuration on advanced multi-die package. Journal of Engineering Research and Reports. 2020;12(4);1-5.