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New design for a certain issue in semiconductor industry is another way to modify the standard configuration into specified limit or to make a possible solution of the problem. This paper presents a new modified design for wirebond top plate with a bias platform structure that will maintain a consistent second bond into a leadframe leads with half-etch configuration on quad-flat no-leads (QFN) packages especially in wirebond process. This paper used a side by side comparison to proof that the new design is better than the older design. With the new specialized wire clamp and top plate design, parts per million (PPM) level performances is improved by almost 90%.
Sumagpang A, Gomez FR. Line stressing critical processes optimization of scalable package passive device for successful production ramp-up. Journal of Engineering Research and Reports. 2018; 3(1):1-13.
STMicroelectronics. Au wire for thermo-compression ultrasonic and thermosonic wire bonding operation. rev. 61.0; 2019.
Geng H. Semiconductor manufacturing handbook. 1st ed., McGraw-Hill Education, USA; 2005.
STMicroelectronics. Assembly and EWS design rules for wire bond Interconnect dice. rev. 53.0; 2018.
Bacquian BC, Gomez FR. A study of vacuum efficiency for silicon on insulator wafers. Journal of Engineering Research and Reports. 2019;6(1):1-6.
May GS, Spanos CJ. Fundamentals of semiconductor manufacturing and process control. 1st ed., Wiley-IEEE Press, USA; 2006.
Gomez FR, Mangaoang T. Elimination of ESD events and optimizing waterjet deflash process for reduction of leakage current failures on QFN-mr leadframe devices. Journal of Electrical Engineering, David Publishing Co. 2018;6(4):238-243.
Doering R, Nishi Y. Handbook of semiconductor manufacturing technology. 2nd Ed., CRC Press, USA; 2007.