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In every new technology developed and introduced to the manufacturing floor, particularly in the wafer preparation, entails problems that later induce defects affecting the wafer yield. This paper discusses the optimization of wafer preparation parameters, particularly the tensionless backgrinding tape lamination and DAF cut vacuum control, that mitigates wafer yield detractors such as edge cut, kerf shift and dice pop-out. Based on the evaluation results, tensionless backgrinding lamination affects the kerf shifting and edge cutting, and with proper vacuum control to attain zero dice pop-out process.
May GS, Spanos CJ. Fundamentals of semiconductor manufacturing and process control. 1st ed., Wiley-IEEE Press, USA; 2006.
Sumagpang A, Gomez FR. A methodical approach in critical processes optimization of new scalable package semiconductor device for ESD applications. Asian Journal of Engineering and Technology. 2018;6(6): 78-87.
Geng H. Semiconductor manufacturing handbook. 1st ed., McGraw-Hill Education, USA; 2005.
Disco Corporation. Dicing before grinding (DBG) process.
Rodriguez R, Gomez FR. Pick and place process optimization for thin semiconductor packages. Journal of Engineering Research and Reports. 2019;4(2):1-9.
STMicroelectronics. Work instruction for tape/DAF and glue diebond process. rev. 66.0; 2018.
Koechner W. Solid-state laser engineering. 6th ed., Springer-Verlag New York, USA; 2006.
Bacquian BC, Gomez FR. A study of wafer backgrinding tape selection for SOI wafers. Journal of Engineering Research and Reports. 2019;6(2)1-6.
Huang HH, Wey J. Research on the high-speed pick and place device for die bonders. 8th IEEE International Conference on Control and Automation. 2010;2:2.