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Wafer passivation or the protective layer of the internal circuitry of the die plays a major role of providing protection and the isolation of electrical stability of the active circuit on the top area of the wafer. Passivation is normally a screen of an oxide layer on the surface of the silicon wafer or the carrier of internal circuitry of the die. Passivation is normally in the form of polyimide or a glass material. From the wafer structure, it is important to cover the active circuit to ensure no other noises will be induced to the wafer. Inclusion of the passivation layer will help maximize the functionality of the semiconductor device thus eliminating noises coming from the external sources.
As the integrated circuit (IC) package goes thinner, the requirement of having the active circuit or the die thinner is the main concern during the wafer preparation process. Wafer backgrinding or wafer thinning is the focal process involved to satisfy such requirement. Prior performing the wafer thinning process, the application of tape, normally in a form of polyolefin or polyvinyl chloride should be performed to eliminate contamination and protects the active layer of the wafer during the process. However, there should be enough adhesion between the wafer and the thinning tape itself. High adhesion strength may lead to adhesive remains or worst, passivation will be peeled off from the active layer of the wafer.
Adhesion to the passivation layer should be properly evaluated and monitored in such way that will eliminate adhesive remains during detaping process after wafer thinning. The effect of adhesion strength could be predicted by properly selecting thinning or protective tape to be used. Higher adhesion strength could be achieved but due to criticality of passivation to tape adhesion, ultra-violet (UV) process should be included to substantially decreased the adhesion. The importance of UV exposure is also discussed on this paper.
Krakauer D. Digital isolation offers compact, low-cost solutions to challenging design problems. Analog Dialogue. 2006; 40.
STMicroelectronics. Visual criteria for sawed wafers and dice. rev. 26.0; 2019.
STMicroelectronics. Assembly and EWS design rules for wire bond Interconnect dice. rev. 53.0; 2018.
Bacquian BC, Gomez FR. A study of wafer backgrinding tape selection for SOI wafers. Journal of Engineering Research and Reports. 2019;6(2):1-6.
Combs E. The back-end process: Step 3 - Wafer Backgrinding; 2002.
“Wafer breakage due to backgrinding”. The Cutting Edge Technical Newsletter; 2008.
Sumagpang A, Gomez FR. Line stressing critical processes optimization of scalable package passive device for successful production ramp-up. Journal of Engineering Research and Reports. 2018; 3(1):1-13.
Bacquian BC, Gomez FR. A study of vacuum efficiency for silicon on insulator wafers. Journal of Engineering Research and Reports. 2019;6(1):1-6.
Gomez FR, Mangaoang T. Elimination of ESD events and optimizing waterjet deflash process for reduction of leakage current failures on QFN-mr leadframe devices. Journal of Electrical Engineering, David Publishing Co. 2018;6(4):238-243.