Main Article Content
The continuous development and trends on thinner semiconductor packages have become the focus in the semiconductor industry. The necessity of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the backgrinding process, itself.
Wafer warpage is one of the main concerns during the backgrinding process. Wafer warpage varies depending on the wafer backgrinding stress and backgrinding tape (hereinafter referred to as BG tape) tension. Hence, tension between the surface protective tape and the wafer should be considered an important and critical item to consider during BG tape selection.
Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior backgrinding. Evaluating the effect of BG tape selection to eliminate such warpage is discussed on this paper.
Wosinski L, Wang Z, Tang Y. Interfacing of silicon-on-insulator nanophotonic circuits to the real world. 12th International Conference on Transparent Optical Networks; 2010.
Mendez H. Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications; 2009.
Chen CL, Chen CK, Yost DR, Knecht JM, Wyatt, PW, Burns JA, Warner K, Gouker PM, Healey P, Wheeler B, Keast CL. Wafer-scale 3D integration of silicon-on-insulator RF amplifiers. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems; 2009.
“Wafer Breakage Due to Backgrinding”, The Cutting Edge Technical Newsletter; 2008.
Doering R, Nishi Y. Handbook of semi-conductor manufacturing technology. 2nd ed., CRC Press, USA; 2007.
Geng H. Semiconductor manufacturing handbook. 1st ed., McGraw-Hill Education, USA; 2005.
Combs E. The back-end process: Step 3 - Wafer backgrinding; 2002.
Sumagpang A, Gomez FR. Line stressing critical processes optimization of scalable package passive device for successful production ramp-up. Journal of Engineering Research and Reports. 2018; 3(1):1-13.
Gomez FR. Improvement on leakage current performance of semiconductor IC packages by eliminating ESD events. Asian Journal of Engineering and Technology. 2018;6(5).